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written in SystemVerilog
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
tenstorrent / riscv-ocelot
Forked from riscv-boom/riscv-boomOcelot: The Berkeley Out-of-Order Machine With V-EXT support
implementation of opencv sgbm(disparity map extract) on FPGA