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PakFPU Public
Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.
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RISCV Public
32-bit soft RISCV processor for FPGA applications
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AES-256-Verilog Public
Synthesisable AES 256 Verilog Implementation
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RISCV-Compliant-Divider Public
Synthesisable RISCV 32bit Divider Verilog Implementation
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AES-256-Matlab Public
AES 256 Implementation in Matlab
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SM4-Verilog Public
Synthesizable SM4 Verilog Implementation
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SM4-Matlab Public
SM4 Encryption Implementation in Matlab
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OpenCV-Maze-Solving Public
Solving a maze using OpenCV and path finding algorithms
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Water-Management-System Public
A device that monitors ad controls water consumption in public washrooms
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