《Hello 算法》：动画图解、一键运行的数据结构与算法教程。支持简中、繁中、English、日本語，提供 Python, Java, C++, C, C#, JS, Go, Swift, Rust, Ruby, Kotlin, TS, Dart 等代码实现

A fast reverse proxy to help you expose a local server behind a NAT or firewall to the internet.

🌩 Self-hosted file management and sharing system, supports multiple storage providers

Latex code for making neural networks diagrams

RT-Thread is an open source IoT Real-Time Operating System (RTOS). https://rt-thread.github.io/rt-thread/

Practice on cifar100(ResNet, DenseNet, VGG, GoogleNet, InceptionV3, InceptionV4, Inception-ResNetv2, Xception, Resnet In Resnet, ResNext,ShuffleNet, ShuffleNetv2, MobileNet, MobileNetv2, SqueezeNet…

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Ultra Fast Structure-aware Deep Lane Detection (ECCV 2020)

Verilog AXI components for FPGA implementation

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Brevitas: neural network quantization in PyTorch

RTX HDR modded into MPC-VideoRenderer.

Zotero Add-on Market | Zotero插件市场 | Browsing, installing, and reviewing plugins within Zotero

Berkeley's Spatial Array Generator

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1

An open-source microcontroller system based on RISC-V

A template project for beginning new Chisel work

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A LaTeX Template for Dissertation Writing at the University of Electronic Science and Technology of China Since 2024

Pytorch实现：使用ResNet18网络训练Cifar10数据集，测试集准确率达到95.46%(从0开始，不使用预训练模型)

UVM examples and projects

GPGPU supporting RISCV-V, developed with verilog HDL

AMBA bus generator including AXI, AHB, and APB

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching

Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM

An almost empty chisel project as a starting point for hardware design

A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA