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GPGPU supporting RISCV-V, developed with verilog HDL
A LaTeX Template for Dissertation Writing at the University of Electronic Science and Technology of China Since 2024
Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
A template project for beginning new Chisel work
An almost empty chisel project as a starting point for hardware design
Fine-tuning Vision Language Models with Graph-based Knowledge for Explainable Medical Image Analysis (MICCAI 2025)
wa-kakalala / cnn_hardware_acclerator_for_fpga
Forked from sumanth-kalluri/cnn_hardware_acclerator_for_fpgaThis is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
An open-source microcontroller system based on RISC-V
A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1
Practice on cifar100(ResNet, DenseNet, VGG, GoogleNet, InceptionV3, InceptionV4, Inception-ResNetv2, Xception, Resnet In Resnet, ResNext,ShuffleNet, ShuffleNetv2, MobileNet, MobileNetv2, SqueezeNet…
RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.
A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
This is a simulation for the behaviour of Zigbee wireless network using MATLAB
AI-Powered Hardware Design & Verification Copilot
Zotero Add-on Market | Zotero插件市场 | Browsing, installing, and reviewing plugins within Zotero
"EVENet: Evidence-based Ensemble Learning for Uncertainty-aware Brain Parcellation using Diffusion MRI"
Verilog AXI components for FPGA implementation
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
A fast reverse proxy to help you expose a local server behind a NAT or firewall to the internet.
High-performance systolic-array accelerator for FP32 matrix multiplication in deep learning.
Run your Nasal code online! This project is based on Valkmjolnir's Nasal Interpreter. https://github.com/ValKmjolnir/Nasal-Interpreter
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
《Hello 算法》：动画图解、一键运行的数据结构与算法教程。支持 Python, Java, C++, C, C#, JS, Go, Swift, Rust, Ruby, Kotlin, TS, Dart 代码。简体版和繁体版同步更新，English version in translation
Brevitas: neural network quantization in PyTorch