Functional Coverage and Constrained Randomization Extensions for Cocotb

Xilinx/AMD FPGA & MPSoC Vivado design skill for Claude — covers block design, IP config, XDC constraints, synthesis, implementation and bitstream generation.

AI-powered SystemVerilog development assistant — design, verify, debug, and deliver working RTL with natural language.

A port of FreeRTOS for the RISC-V ISA

'Classic' FreeRTOS distribution. Started as Git clone of FreeRTOS SourceForge SVN repo. Submodules the kernel.

FreeRTOS kernel files only, submoduled into https://github.com/FreeRTOS/FreeRTOS and various other repos.

你管这破玩意叫操作系统源码 — 像小说一样品读 Linux 0.11 核心代码

Linux kernel source tree

Your own personal AI assistant. Any OS. Any Platform. The lobster way. 🦞

The Ultra-Low Power RISC-V Core

Berkeley's Spatial Array Generator

UVM examples and projects

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

GPGPU supporting RISCV-V, developed with verilog HDL

A LaTeX Template for Dissertation Writing at the University of Electronic Science and Technology of China Since 2024

AXI 总线验证 模块

Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM

A template project for beginning new Chisel work

An almost empty chisel project as a starting point for hardware design

Fine-tuning Vision Language Models with Graph-based Knowledge for Explainable Medical Image Analysis (MICCAI 2025).

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

An open-source microcontroller system based on RISC-V

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1

Practice on cifar100(ResNet, DenseNet, VGG, GoogleNet, InceptionV3, InceptionV4, Inception-ResNetv2, Xception, Resnet In Resnet, ResNext,ShuffleNet, ShuffleNetv2, MobileNet, MobileNetv2, SqueezeNet…

RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.

A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA

A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching

This is a simulation for the behaviour of Zigbee wireless network using MATLAB