Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog AXI components for FPGA implementation

GPGPU supporting RISCV-V, developed with verilog HDL

RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.

High-performance systolic-array accelerator for FP32 matrix multiplication in deep learning.

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs