Sigil Logic
- 7 followers
- United States of America
- https://sigillogic.com/
- company/sigil-logic
- contact@sigillogic.com
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Repositories
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Sail RISC-V model
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A formalization of the CHERIoT+RTOS model
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A DSL for formal verification of hardware and software systems using Rocq/Coq.
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Sigil Logic's public releases for AIVHAI (AI Verified Hardware for AI): red-team packages, assurance cases, and pinned evidence. One commit per release.
- riscv-iopmp Public Forked from riscv-non-isa/riscv-iopmp
This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.
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