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core-v-docs Public
Forked from openhwfoundation/programsDocumentation for the OpenHW Group's set of CORE-V RISC-V cores
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cv32e40p Public
Forked from openhwfoundation/cv32e40pCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog Other UpdatedNov 29, 2024 -
cv32e40x Public
Forked from openhwfoundation/cv32e40x4 stage, in-order, compute RISC-V core based on the CV32E40P
SystemVerilog Other UpdatedOct 30, 2024 -
cv32e40s Public
Forked from openhwfoundation/cv32e40s4 stage, in-order, secure RISC-V core based on the CV32E40P
SystemVerilog Other UpdatedDec 5, 2023 -
obi Public
Forked from openhwfoundation/obiRepository that maintain the OpenBus Interface spec
UpdatedApr 26, 2023 -
riscv-dbg Public
Forked from pulp-platform/riscv-dbgRISC-V Debug Support for our PULP Cores
SystemVerilog Other UpdatedSep 13, 2022 -
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core-v-verif Public
Forked from openhwfoundation/core-v-verifFunctional verification project for the CORE-V family of RISC-V cores.
Assembly Other UpdatedApr 7, 2022 -
ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
SystemVerilog Apache License 2.0 UpdatedApr 16, 2021 -
riscv-isa-manual Public
Forked from riscv/riscv-isa-manualRISC-V Instruction Set Manual
TeX Creative Commons Attribution 4.0 International UpdatedApr 13, 2021 -
fpnew Public
Forked from openhwfoundation/cvfpuParametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
SystemVerilog Other UpdatedApr 20, 2020 -
core-v-cores Public
Forked from openhwfoundation/core-v-coresCORE-V Family of RISC-V Cores
UpdatedFeb 11, 2020
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