Skip to content
View TogashiHan's full-sized avatar

Block or report TogashiHan

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
8 results for sponsorable starred repositories
Clear filter

The book "Performance Analysis and Tuning on Modern CPU"

TeX 3,354 235 Updated Jun 9, 2025

This is an online course where you can learn and master the skill of low-level performance analysis and tuning.

C++ 3,326 326 Updated Nov 5, 2025

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

VHDL 143 23 Updated Oct 14, 2025

Useful UVM extensions

SystemVerilog 25 6 Updated Jul 10, 2024

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

Assembly 133 28 Updated Sep 28, 2025

32-bit Superscalar RISC-V CPU

Verilog 1,118 195 Updated Sep 18, 2021

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

C 12,186 6,308 Updated Nov 5, 2025

AMBA AXI VIP

SystemVerilog 426 119 Updated Jun 28, 2024