The book "Performance Analysis and Tuning on Modern CPU"

This is an online course where you can learn and master the skill of low-level performance analysis and tuning.

This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate …

RISC-V IOMMU Specification

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

A source-level simulator for multi-core system

RiVEC Bencmark Suite

A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.

VeeR EL2 Core

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Instruction Set Generator initially contributed by Futurewei

Binarized Convolutional Neural Networks on Software-Programmable FPGAs (FPGA'17)

UVM AHB VIP

Useful UVM extensions

Unit tests generator for RVV 1.0

WAL enables programmable waveform analysis.

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

Locus site for Public Review of Several RISC-V ISA Formal Specs

Get up and running with OpenAI gpt-oss, DeepSeek-R1, Gemma 3 and other models.

The missing test suite for RISC-V V extension.

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

The OpenPiton Platform

RISC-V Formal Verification Framework

Chisel: A Modern Hardware Design Language

RISC-V Nexus Trace TG documentation and reference code

Self checking RISC-V directed tests

PLIC Specification