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tenstorrent / riscv-ocelot
Forked from riscv-boom/riscv-boomOcelot: The Berkeley Out-of-Order Machine With V-EXT support
This is an online course where you can learn and master the skill of low-level performance analysis and tuning.
Chisel: A Modern Hardware Design Language
Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate …
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
Functional verification project for the CORE-V family of RISC-V cores.
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Random instruction generator for RISC-V processor verification
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
The book "Performance Analysis and Tuning on Modern CPU"
Self checking RISC-V directed tests
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform