Get up and running with OpenAI gpt-oss, DeepSeek-R1, Gemma 3 and other models.

Free ChatGPT Site List 这儿为你准备了众多免费好用的ChatGPT镜像站点

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Chisel: A Modern Hardware Design Language

Yosys Open SYnthesis Suite

The book "Performance Analysis and Tuning on Modern CPU"

This is an online course where you can learn and master the skill of low-level performance analysis and tuning.

Spike, a RISC-V ISA Simulator

cocotb: Python-based chip (RTL) verification

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Random instruction generator for RISC-V processor verification

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

32-bit Superscalar RISC-V CPU

Working draft of the proposed RISC-V V vector extension

RISC-V Cores, SoC platforms and SoCs

RISC-V Opcodes

The OpenPiton Platform

GPL v3 2D/3D graphics engine in verilog

RISC-V Formal Verification Framework

Functional verification project for the CORE-V family of RISC-V cores.

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

AMBA AXI VIP

Binarized Convolutional Neural Networks on Software-Programmable FPGAs (FPGA'17)

VeeR EL2 Core

Instruction Set Generator initially contributed by Futurewei

A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.

RISC-V Zve32x Vector Coprocessor

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support