Yosys Open SYnthesis Suite

Learning FPGA, yosys, nextpnr, and RISC-V

Icarus Verilog

Verilog to Routing -- Open Source CAD Flow for FPGA Research

你还在为有刷电机的高噪声、低响应速度和低寿命而烦恼吗？这个项目是一个20块钱就能搞定的FOC无刷电机控制方案！This project is a FOC (Field Oriented Control) BLDC Motor control scheme that can be done for 3$!

cmix is a lossless data compression program aimed at optimizing compression ratio at the cost of high CPU/memory usage.

现代图形引擎入门指南

MQSim is a fast & accurate simulator for modern multi-queue (MQ) and SATA SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and full end-to-end…

A voxel game/Minecraft clone for the iCE40 UP5K FPGA

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

Game Closure Image Format

state-of-the-art lossless audio compression

Trabalho de Graduação

A library turn Curie Core boards(Arduino/Genuino 101) into a Bluetooth Keyboard.

Vitis 部署加速器工作流介绍

Benchmarks for High-Level Synthesis

LOCO-ANS: An optimization of JPEG-LS using an efficient and low complexity coder based on ANS

这是一个用C++实现的Markdown解释器，生成html代码

Hiroki Kojima, Yasuyo Kita, Ichiro Matsuda, Susumu Itoh, Yusuke Kameda, Kyohei Unno, Kei Kawamura: "Improved Probability Modeling for Lossless Image Coding Using Example Search and Adaptive Predict…