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About Me

Hello!👋(●'◡'●) I'm Yi Ding.

About Me:

  • 🔭 I'm currently studying EE (Electronic Engineering) at UCAS
  • 📫 How to reach me: dingyi233@mails.ucas.ac.cn
  • ⚡ Fun fact: I used to be a semi-professional soccer player as a national level two athlete.
  • 🌱 I am currently learning about tranceivers/SerDes.

My Technology Stack:

  • LaTex
  • MATLAB
  • C Programming
  • MCU (Micro-Controller Unit)
  • PCB Layout
  • Analog Circuit Design
  • LTspice (ANALOG DEVICES)
  • Cadence Virtuoso
  • Analog IC Design (OPA, OTA, BGR, LDO, etc.)
  • Mixed-Signal IC Design (DAC, VCO, PLL, CDR, etc.)
  • Verilog, Verilog-A/AMS

Anurag's GitHub stats

Anurag's GitHub stats

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I Mostly Code in TeX

TeX                      4 repos             ███████░░░░░░░░░░░░░░░░░░   28.57 % 
C                        4 repos             ███████░░░░░░░░░░░░░░░░░░   28.57 % 
MATLAB                   3 repos             █████░░░░░░░░░░░░░░░░░░░░   21.43 % 
JavaScript               2 repos             ████░░░░░░░░░░░░░░░░░░░░░   14.29 % 
Verilog                  1 repo              ██░░░░░░░░░░░░░░░░░░░░░░░   07.14 % 

Last Updated on 2026.07.23 19:53 UTC

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