Search results

Implementing Croc on GateMate CCGM1A1 requires excessive time to route

Status: Open.

#1615 In YosysHQ/nextpnr;

· thommythomaso opened on Dec 12, 2025

Reduce the placed and routed SVG file

Status: Open.

#1610 In YosysHQ/nextpnr;

· pat-pgt opened on Dec 1, 2025

shift register with enable using SLICE_LUTX.

Status: Open.

#1601 In YosysHQ/nextpnr;

· Sebastien-EU opened on Nov 19, 2025

Failed to find a route for arc 0 of net

Status: Open.

#1599 In YosysHQ/nextpnr;

· CristhoferHenriquez opened on Nov 15, 2025

[ECP5] Missing pip on GUI?

Status: Open.

#1590 In YosysHQ/nextpnr;

· krisdamk opened on Oct 21, 2025

[wishlist] Building little and big endian versions of the chipdb in parallel

Status: Open.

#1570 In YosysHQ/nextpnr;

· GyrosGeier opened on Oct 5, 2025

Tests don't work with -DEXTERNAL_CHIPDB=ON

Status: Open.

#1567 In YosysHQ/nextpnr;

· GyrosGeier opened on Oct 4, 2025

OpenMP option default setting

Status: Open.

#1553 In YosysHQ/nextpnr;

· Tectu opened on Sep 8, 2025

recommended version/setup for Kintex-7?

Status: Open.

#1522 In YosysHQ/nextpnr;

· juanschroeder opened on Jul 24, 2025

ECP5 IDDR71B not working as expected

Status: Open.

#1521 In YosysHQ/nextpnr;

· dwalton65 opened on Jul 24, 2025

[Reature Request] Automatic assignment of 'regular' clock signal to a global clock net.

Status: Open.

#1515 In YosysHQ/nextpnr;

· zapta opened on Jul 8, 2025

nextpnr fails when a ECLKSYNC component is placed in a PLL feedback path

Status: Open.

#1511 In YosysHQ/nextpnr;

· dwalton65 opened on Jul 1, 2025