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Post-placement 'Max frequency' report is unlabelled and indistinguishable from the post-route result

Status: Open.

#1808 In YosysHQ/nextpnr;

· turian opened on Sep 22, 2026

gowin: BRAM timing model adds DP port-B address checks to the SPX9 variant

Status: Open.

#1803 In YosysHQ/nextpnr;

· hugoferreira opened on Sep 18, 2026

gatemate/CC_PLL: LOCK_REQ default does not match UG1001 primitives library PDF

gatemateCologne Chip CCGM1 (GateMate)Cologne Chip CCGM1 (GateMate)

Status: Open.

#1790 In YosysHQ/nextpnr;

· MartinHanl opened on Sep 2, 2026

Region constraints are hard to use on a large design

Status: Open.

#1784 In YosysHQ/nextpnr;

· colneech-dev opened on Aug 22, 2026

[Req] Please add gui rendering for gowin devices

enhancementNew feature or requestNew feature or request

Status: Open.

#1762 In YosysHQ/nextpnr;

· Lucretia opened on Jul 31, 2026

Generic getGroupByName() accepts unknown group names

Status: Open.

#1760 In YosysHQ/nextpnr;

· daleydeng opened on Jul 29, 2026

Xilinx LUT permutation fixup mixes paired O5/O6 mappings

Status: Open.

#1757 In YosysHQ/nextpnr;

· daleydeng opened on Jul 29, 2026

gatemate: constant drivers cause inputs ports to be renamed ""

gatemateCologne Chip CCGM1 (GateMate)Cologne Chip CCGM1 (GateMate)

Status: Open.

#1756 In YosysHQ/nextpnr;

· Jaspi10 opened on Jul 24, 2026

iCE40: hold time violation with no clear way to resolve it

Status: Open.

#1753 In YosysHQ/nextpnr;

· whitequark opened on Jul 23, 2026

himbachel/gowin: Timing constraint does not properly copied between net

Status: Open.

#1748 In YosysHQ/nextpnr;

· perillamint opened on Jul 14, 2026

GateMate: missing timing check from and to IO FF.

gatemateCologne Chip CCGM1 (GateMate)Cologne Chip CCGM1 (GateMate)

Status: Open.

#1741 In YosysHQ/nextpnr;

· moffel opened on Jun 25, 2026

himbaechel/gowin: IO_PORT is silently ignored when on the same line as IO_LOC (IO_TYPE/PULL_MODE not applied)

Status: Open.

#1738 In YosysHQ/nextpnr;

· pbella opened on Jun 18, 2026