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Linux tools and examples for OPTIGA™ Trust V1/V3 security solution
Yocto/OE BSP layer for the Raspberry Pi boards
OSS implementation of the TCG TPM2 Software Stack (TSS2)
Overview of the OPTIGA™ Trust M product family
Setup and examples of using OPTIGA™ TPM backed Linux Trusted and Encrypted Keys
Simple to use GUI tool for Infineon OPTIGA TPM 2.0
STM32 examples for USART using DMA for efficient RX and TX transmission
STM32 sample application showing how to use actions for CI
GPIO Bare metal drivers for stm32 f4 family of microcontrollers written in C from scratch .The driver allows user to configure the gpio pins of stm32 microcontroller in Input Mode , Output mode , A…
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…
A digital logic designer and circuit simulator.
Digital logic design tool and simulator
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
Bare-Metal Embedded C Programming by Packt Publishing
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
Verilog Ethernet components for FPGA implementation
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
lwIP TCP/IP Stack and FreeRTOS runs on STM32 F7 Series microcontroller
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
Open-source RISC-V microcontroller for embedded and FPGA applications
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Simple implementation of I2C interface written on Verilog and SystemC