VHDL 2008/93/87 simulator

VUnit is a unit testing framework for VHDL/SystemVerilog

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

A huge VHDL library for FPGA and digital ASIC development

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

VHDL synthesis (based on ghdl)

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Space Invaders game implemented with VHDL

RTL implementation of components for DVB-S2

FPGA-based HDMI ambient lighting

A FPGA core for a simple SDRAM controller.

👇 Add capacitive touch buttons to any FPGA!

A JSON library implemented in VHDL.

Caffe to VHDL

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

A translation of the Xilinx XPM library to VHDL for simulation purposes

VHDL-2008 Support Library

cryptography ip-cores in vhdl / verilog

ulx3s ghdl examples

Standard and Curated cores, tested and working.