Modular hardware build system

SiliconCompiler Design Gallery

An Automata Learning Library Written in Python

A tiny FABulous FPGA for TTIHP26a

Self-contained RTL to GDS flow for simple chip designs

wafer.space GF180MCU Run 1

An attempt to recreate the RP2040 PIO in an FPGA

3.3V SRAM macros for GF180MCU, based on the original 5V SRAM macros.

ASIC implementation flow infrastructure, successor to OpenLane

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Project template for wafer.space MPW runs using the gf180mcu PDK

Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

Hardware transactions library for Amaranth

The official PCB for HeiChips 2025

Multiplication and accumulation acceleration with 4 bit interface for the FazyRV RISC-V core

Virtual Prototype for identifying Application Specific Hardware Optimization candidates

The template for the HeiChips 2025 hackathon

HeiChips 2025 Tapeout on IHP SG13G2 130nm process

State-of-the-Art Source Code Plagiarism & Collusion Detection. Check for plagiarism in a set of programs.

CMake based hardware build system

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Native32 reverse engineering and emulation project

Digital Design with Chisel

An open-source implementation of the VADL processor description language.

interactive visualization of 5 popular gradient descent methods with step-by-step illustration and hyperparameter tuning UI

Python-based Hardware Design Processing Toolkit for Verilog HDL

Greyhound on IHP SG13G2 0.13 μm BiCMOS process

3-stage RV32IMACZb* processor with debug