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written in SystemVerilog
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Verilator open-source SystemVerilog simulator and lint system
OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Test suite designed to check compliance with the SystemVerilog standard.
The multi-core cluster of a PULP system.
A naive verilog/systemverilog formatter