🎓 Undergraduate Student in Integrated Circuit Design
I am passionate about Digital IC Design, RTL Design, FPGA Prototyping, and Design Verification. I enjoy building reliable digital hardware and continuously improving my engineering skills through hands-on projects.
- 🎯 Interested in RTL Design and FPGA Development
- 💻 Working with Verilog HDL and learning SystemVerilog
- 🔬 Currently developing an IEEE-754 Floating Point Unit (FPU)
- 📚 Continuously studying Computer Architecture and Digital Design
- Verilog HDL
- SystemVerilog (Learning)
- C
- Python
- Vivado
- ModelSim
- Git
- GitHub
A modular IEEE-754 single-precision Floating Point Unit implemented in Verilog HDL.
Current Features
- Floating-point Addition
- Floating-point Subtraction
- Floating-point Multiplication
- Non-pipeline Architecture
- 2-stage Pipeline
- 3-stage Pipeline
- FPGA Implementation on Xilinx Zynq-7010 (EBAZ4205)
Repository:
➡️ Coming Soon
- RTL Design
- FPGA Design
- Digital IC Design
- ASIC Design
- Design Verification
- Advanced SystemVerilog
- UVM Fundamentals
- FPGA Timing Closure
- Digital IC Design Flow
- LinkedIn: (Coming Soon)
- Email: (Coming Soon)
Thanks for visiting my GitHub!