PicoRV32 - A Size-Optimized RISC-V CPU

SERV - The SErial RISC-V CPU

RISC-V CPU Core (RV32IM)

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

3-stage RV32IMACZb* processor with debug

A tiny Open POWER ISA softcore written in VHDL 2008

Open source retro ISA video card

Verilog SDRAM memory controller

Mega Drive/Genesis core written in Verilog

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

Analogue Pocket Neogeo Core compatible with openFPGA

iCESugar series FPGA dev board

Compact FPGA game console

NeoGeo for MiSTer

A template for getting started with FPGA core development

FPGA implementation of Sega Genesis for Analogue Pocket.

A Full Hardware Real-Time Ray-Tracer

The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.

Cycle-Accurate MC6809/E implementation, Verilog

Simulation only cartridge NeoGeo hardware definition

Digital Interpolation Techniques Applied to Digital Signal Processing

Verilog module compatible with Yamaha OPL chips

BeagleBone HW, SW, & FPGA Development

SNK NeoGeo core for the MiSTer platform

TV80 Z80-compatible microprocessor

Sega Master System emulator written in Verilog

Example Verilog code for Ulx3s

Atari ST/STe for MiSTer

An FPGA based handheld NES system built around the Spartan 6 and the Spartan Mini development board.

PicoRV32 - A Size-Optimized RISC-V CPU