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OpenLane Public
Forked from The-OpenROAD-Project/OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Python Apache License 2.0 UpdatedSep 15, 2025 -
fpgai_compiler Public
Forked from umutcanaltin/fpgai_compilerONNX Compiler for deep learning inference in FPGA's
Python Other UpdatedFeb 24, 2025 -
fpga-ml-accelerator Public
Forked from thedatabusdotio/fpga-ml-acceleratorThis repository hosts the code for an FPGA based accelerator for convolutional neural networks
Verilog UpdatedJun 20, 2024 -
AD9910 Public
Forked from snu-quiqcl/AD9910AD9910 codes for evaluation board
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AccDNN Public
Forked from IBM/AccDNNA compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Verilog Apache License 2.0 UpdatedDec 2, 2019 -
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