OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

ONNX Compiler for deep learning inference in FPGA's

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

AD9910 codes for evaluation board

AD9910 codes for evaluation board