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neeti06/README.md

πŸ‘‹ Hi, I’m Neeti Kushwaha

πŸŽ“ Electronics Engineering Student (4th Year)
πŸ’‘ Aspiring VLSI / Digital Design Engineer
🧠 Strong in Verilog HDL, RTL Design & Xilinx Vivado
πŸš€ Passionate about hardware-centric problem solving & simulation-based design

Focused on building strong RTL fundamentals for the semiconductor industry.

🌐 Socials:

Instagram LinkedIn email


🧠 Technical Expertise (VLSI-Oriented)

πŸ”§ HDL & EDA Tools

  • Verilog HDL (RTL Coding)
  • Xilinx Vivado (Simulation & Synthesis)
  • Testbench writing & waveform analysis
  • Modular & readable RTL design practices

βš™οΈ Core Electronics & Architecture

  • Digital Electronics
  • Computer Architecture
    (Register File, FIFO, FSM)
  • Control Systems (fundamentals)

πŸ’» Programming & Embedded

  • C (Basics)
  • Embedded C
  • HTML & CSS

πŸ“‚ Highlighted Projects

πŸ”Ή Register File Design (Verilog)

  • Designed an 8Γ—8 Register File at RTL level
  • Supports synchronous write & asynchronous read
  • Verified using self-written testbench in Vivado
  • Emphasis on clean architecture, scalability & correctness

πŸ”Ή Arduino-Based Hand Gesture Controlled Robot

  • Implemented using Arduino, MPU6050 & HC-05 Bluetooth
  • Gesture-controlled robotic arm and motion system
  • Integrated motor drivers, sensors & power management

πŸ”Ή Home Automation System

  • Built using microcontroller, relay modules & Wi-Fi
  • Enabled wireless control of appliances
  • Practical exposure to real-world embedded systems

πŸ§ͺ Current Focus

  • Intermediate RTL & Verilog design projects
  • Strengthening digital fundamentals for VLSI roles
  • Preparing for semiconductor & core electronics internships

🎯 Career Objective

To start my career in the VLSI / Semiconductor industry, contributing as a
Digital Design / RTL / Verification-oriented Engineer with strong fundamentals.


🀝 Connect With Me

πŸ’Ό LinkedIn: https://www.linkedin.com/in/neeti-kushwaha-ece/
πŸ“§ Email: 06neeti02@gmail.com


⭐ If my projects align with your interests, feel free to explore or connect!

Popular repositories Loading

  1. Register-File-verilog-Xininx Register-File-verilog-Xininx Public

    8Γ—8 Register File implemented in Verilog HDL with testbench verification using Xilinx Vivado.

    Verilog

  2. neeti06 neeti06 Public

  3. Traffic-Light-Controller-VLSI Traffic-Light-Controller-VLSI Public

    Verilog