opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A small, light weight, RISC CPU soft core

Verilog PCI express components

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

This is mainly a simulation library of xilinx primitives that are verilator compatible.

An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization

Chisel Project for Integrating RTL code into SDAccel