130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A curated list of Computer Architecture and Systems resources

Quick & Flexible Rack-Scale Computer Architecture Simulator

Image processing on FPGA using verilog

Implementing a RISC-V CPU on FPGA(Cyclone II)

Serial 32bit RISCV Core

Read-only Git mirror of the Mercurial gecko repositories at https://hg.mozilla.org. How to contribute: http://bit.ly/contribute-code

Read-only Git mirror of the Mercurial gecko repositories at https://hg.mozilla.org. How to contribute: http://bit.ly/contribute-code

Configure your beagle device

Responsive, Sticky and Customizable Navbar

SRA's seminar on Introduction to Computer Vision Fundamentals

A customized RISCV core made using verilog