Source code for the Ramulator 2.0, DAMOV and Standalone Ramulator used in our ISPASS 2026 paper "Cleaning up the Mess: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0". Paper: http…

PaCRAM is a technique that reduces the performance and energy overheads of the existing RowHammer mitigation mechanisms by carefully reducing the latency of preventive refreshes issued by existing …

A reinforcement learning based policy to dynamically coordinate off-chip predictor with multiple data prefetchers, as described in the HPCA2026 paper by Bera and Lang et al.: https://arxiv.org/abs/…

The GitHub repository containing all resources used in the 4th Data Prefetching Championship (DPC4), co-located with HPCA 2026.

Chai

Detailed read disturbance (RowHammer and RowPress) characterization of six real HBM2 DRAM chips yielding 23 new observations and 8 new takeaways, as described in the DSN'24 paper https://arxiv.org/…

A comprehensive benchmarking framework for raw nanopore signal analysis, as described by Eris et al. (https://arxiv.org/pdf/2510.03629)

EasyDRAM is an FPGA-based framework for rapid and accurate end-to-end evaluation of DRAM techniques on real DRAM chips. Described in our DSN 2025 paper: https://arxiv.org/abs/2506.10441

Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025

UPMEM-SDK

The official ChampSim version used in 4th Data Prefetching Championship (DPC4). This repository is forked from the ChampSim simulator, officially maintained by researchers from Texas A&M University.

This repository contains the source code of LeakyHammer, our MICRO'25 paper. LeakyHammer is a new class of attacks that leverage the RowHammer mitigation-induced memory latency differences to estab…

Chronus is an on-DRAM-die read disturbance mitigation mechanism that addresses the two major weaknesses of the new industry standard Per Row Activation Counting (PRAC) by eliminating counter update…

Source code for the architectural simulator used for modeling the PUD system proposed in our ICS 2025 paper `Proteus: Achieving High-Performance Processing-Using-DRAM with Dynamic Bit-Precision, Ad…

PIMDAL (PIM Data Analytics Library) is an implementation of DB operators and 5 TPC-H queries on the UPMEM PIM system. Additionally we provide code to generate the TPC-H data and reference implement…

Data and code for the VTS'25 paper "Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies." Described in our VTS 2025 paper: h…

IMPACT is a new framework that leverages Processing-in-Memory (PiM) to amplify data leakage in main memory-based timing attacks. More details: https://arxiv.org/abs/2404.11284

PIM-TC implements a distributed Triangle Counting (TC) algorithm specifically designed for and evaluated on the UPMEM Processing-in-Memory (PIM) architecture. Described in our paper https://arxiv.o…

Ariadne is a new compressed swap scheme for mobile devices that reduces application relaunch latency and CPU usage while increasing the number of live applications for enhanced user experience. Des…

A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (ii) activating a disproportionately large number of DRAM cells…

Rawasm is a patch to the popular miniasm tool. It enables the construction of genome assembly from raw nanopore signals.

MegIS is the first in-storage processing system designed to significantly reduce the data movement overhead of the end-to-end metagenomic analysis pipeline. Described in the ISCA 2024 paper by Mans…

PyGim is the first runtime framework to efficiently execute Graph Neural Networks (GNNs) on real Processing-in-Memory systems. It provides a high-level Python interface, currently integrated with P…

Source code & scripts for distributed machine learning training workloads on a real-world Processing-In-Memory system (i.e., UPMEM). Described in our PACT'24 paper by Rhyner et al. at https://arxiv…

BreakHammer is a technique that reduces the performance overhead of RowHammer mitigation mechanisms by carefully reducing the number of performed RowHammer-preventive actions without compromising s…

A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arxiv.org/pdf/2406.18786

Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input majority operations and 3) copying one row's content to up 31 r…

Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used i…