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A minimal GPU design in Verilog to learn how GPUs work from the ground up
4 stage, in-order, compute RISC-V core based on the CV32E40P
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Final project for CS 429H (computer architecture), fall freshman year. Built over the course of 2 weeks.
BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput and compute density to increase the amount of cores in many-…
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.