An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

CNN acceleration on virtex-7 FPGA with verilog HDL

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

A very primitive but hopefully self-educational CPU in Verilog

5-stage pipelined 32-bit MIPS microprocessor in Verilog

A single-wire bi-directional chip-to-chip interface for FPGAs

UART -> AXI Bridge

The Original Nintendo Gameboy in Verilog

Verilog RTL Design

Verilog for ASIC Design

KISCV, a KISS principle riscv32i CPU

EE577b-Course-Project

Verilog Generation with Reinforcement Learning

DDR2 Memory Controller fit into a low-end CPLD

5 Cycle-accurate Implementation of a pipelined MIPS processor

Verilog model of an asynchronous RISCV CPU