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01-basic-logic-gates Public
Basic Logic Gates in Verilog — AND, OR, NOT, NAND, NOR, XOR, XNOR | Step 1 of 8 toward a 16-bit pipelined RISC processor
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02-combinational-circuits Public
Combinational circuits in Verilog - Adders, Subtractor, MUX, Decoder, Encoder, Comparator and 16-bit ALU. Step 2 of 8 in a VLSI portfolio roadmap building to a 16-bit pipelined RISC processor.
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03-sequential-circuits Public
Sequential circuits in Verilog — Flip-Flops, Registers, Counters, Shift Registers and Synchronous SRAM. Step 3 of 8 in a VLSI portfolio roadmap building to a 16-bit pipelined RISC processor.
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04-finite-state-machines Public
Finite State Machines in Verilog — Moore FSM, Mealy FSM, Traffic Light Controller, Sequence Detector (1011), UART Transmitter, UART Receiver, SPI Master, Debounce Circuit | Step 4 of 8 toward a 16-…
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verilog-eda-automation Public
Python automation framework for RTL regression testing — auto-compiles and simulates Verilog modules, parses PASS/FAIL results, and generates HTML reports
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verilog-hdlbits Public
HDLBits problem solutions in Verilog — structured practice alongside an 8-repo VLSI portfolio
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