VHDL 2008/93/87 simulator

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the fut…

GPL v3 2D/3D graphics engine in verilog

Parallella board design files

Community created parallella projects

A Forth CPU and System on a Chip, based on the J1, written in VHDL

VHDL synthesis (based on ghdl)

A simple RISC-V processor for use in FPGA designs.

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

Basic RISC-V CPU implementation in VHDL.

Space Invaders game implemented with VHDL

A bit-serial CPU written in VHDL, with a simulator written in C.

Various projects for the Nexys4DDR board from Digilent

A pipelined RISCV implementation in VHDL

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

SEGA Genesis/Megadrive core, running on a Altera/Terasic DE1 board.

A simple CPU in VHDL for educational purposes

J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.

VHDL implementation of a MIPS processor for Spartan-6 FPGA