xezim is a SystemVerilog simulator written in Rust designed for experimentation, learning, and exploring AI-assisted chip design workflows.

xezim was previously developed under the name sisSIM. The binary, library, and compiled-artifact magic were renamed in place; behavior is unchanged.

This project explores whether modern tools and AI can dramatically reduce the complexity of building core EDA infrastructure such as simulators.

The simulator parses SystemVerilog source code, builds an internal representation, and executes simulations for combinational and sequential logic.

Traditional EDA tools require very large engineering teams and many years of development.

This project explores a key question:

Can a small team — or even a single engineer with AI assistance — build core EDA tools such as a SystemVerilog simulator?

The simulator is being developed incrementally, starting from simple combinational logic and gradually adding more SystemVerilog features.

Current capabilities include:

• IEEE 1800-2023 grammar by default (--sv2017 opts back to the earlier edition)
• SystemVerilog module parsing
• Signal and net representation
• Continuous assignments
• Basic expression evaluation
• Combinational logic simulation
• Sequential simulation infrastructure
• Test execution framework
• Waveform / trace dumps — VCD ($dumpfile/$dumpvars; IEEE 1800-2017 §21.7, and matches Verilator/Icarus in GTKWave) and XTrace v1.0 (--xtrace, optional zstd compression + scope filtering)
• UVM run-phase execution (Accellera 1800.2-2017 and 1800.2-2020.3.1, with -DUVM_NO_DPI) — a real UVM testbench runs end-to-end: build → connect → topology → run_phase stimulus → sequencer↔driver TLM handshake → packet collection → objection-driven termination → report summary. The reference testbench (GettingVerilatorStartedWithUVM) reaches exact Verilator parity on the 2017 library and runs green on 2020.3.1, and 32/35 UVM 1800.2-2017 example testbenches pass. Multiple top modules (-s hdl_top -s hvl_top) and virtual-interface config_db are supported. See docs/uvm-guide.md.
• UVM 1.2 runtime support, also demonstrated by running the riscv-dv instruction generator end-to-end (random RV32IMC programs that assemble cleanly with riscv64-unknown-elf-as -march=rv32imc_zicsr_zifencei)
• Event-driven edge gating (XEZIM_EVENT_EDGE=1) — opt-in skip of clocked flop fires whose data inputs haven't changed; 1.13-1.30× wall on the C910 / C906 hello / memcpy / cmark benchmarks, correct-by-construction
• DPI-C loading via --dpi-lib <path> — load shared libraries of import "DPI-C" implementations written in C or C++ (e.g. an ISS shim, a custom HDL-backdoor force/release layer, or your own UVM extensions). The repo ships minimal svdpi.h and vpi_user.h so DPI code compiles without a vendor install. See docs/dpi-guide.md.
• Event-control iff guards (LRM §9.4.2.3) — @(posedge clk iff rst_n) is honored in both procedural @ waits and edge-sensitive always blocks: the process resumes only on an edge where the guard holds.
• User-defined nettypes with resolution functions (LRM §6.6.7) — nettype T wire_t with resolver; including Z-skip and built-in resolution.
• Per-module timescales (LRM §3.14, §20.3, §21.3.5) — $time/$realtime scale to the calling module's time unit; timeunit/timeprecision declarations scale delays; $timeformat/%t and $printtimescale are honored; precision down to fs. Modules without a source-level timescale can be assigned one from the CLI (see --module-timescale).
• VPI loading via --vpi-lib <path> (-m) — classic VPI modules run their vlog_startup_routines: system-task/function registration (vpi_register_systf) and design iteration (vpi_iterate/vpi_scan, handle/property access).

These are not part of IEEE 1800 — they are de-facto vendor (Verilog-XL / VCS / Questa / Xcelium) extensions supported for compatibility with existing gate-level and testbench flows. Portable code should not rely on them.

• $deposit(target, value) — sets target to value immediately without installing a persistent driver: the value holds until the next driver transaction overwrites it (on an undriven net it simply sticks). This is a Verilog-XL/VCS system task, not in the LRM. xezim matches the vendor semantics — a variable keeps the deposited value, and a real driver on a net overrides a deposit on its next update.
• Gate-level-simulation CLI flags — +nospecify, +notimingcheck, +delay_mode_zero/+delay_mode_unit, +mindelays/+typdelays/+maxdelays, and the -v/-y/+libext+ library flags — mirror the commercial spellings.

• UVM 1800.2-2020.3.1 runs green — the reference testbench passes against the 2020.3.1 library (UVM_ERROR : 0 / UVM_FATAL : 0, in/out monitors agree). Closing this required a general preprocessor fix (inline `ifdef/`endif mid-line, §22.6), class-body localparam constants, and sequencer-path fixes (process::self(), fork/join_none automatic-variable sharing).
• User-defined nettypes (LRM §6.6.7) — nettype declarations with user resolution functions, Z-skip, and built-in resolution.
• Per-module timescales — $time/$realtime scale to the calling module's unit; timeunit/timeprecision declarations scale delays; $timeformat/%t and $printtimescale honored; sub-ns precision down to fs; new --module-timescale CLI extension for legacy RTL with no source-level timescale.
• String & aggregate conformance fixes — s[i] read/write on string variables (§11.4.13), ref/output queue arguments copy back on return (§13.5.2), %p renders function-local queues/associative arrays (§21.2.1.7), foreach over a string iterates its content length, q = {} clears string queues, and a never-touched module-scope queue reports size() == 0.
• Free functions no longer see the caller's class context (§13.4) — a bare name in a package/module function that collided with a caller class property used to silently alias the property; queue-property access from outside the class (obj.q.push_back(x), %p of obj.q) now resolves correctly.
• Gate-level & structural robustness — multi-dimensional packed arrays of unpacked elements (arr[i][j], §7.4), foreach over negative/descending and packed dimensions (§12.7.3), non-ANSI ports completed by a reg/logic declaration (§23.2.2.1), and per-iteration uniquification of declarations inside nested generate-for loops (for(a) for(b) localparam Idx = f(a,b)).
• Behavioral clocks & PLLs — a clock generator whose delay reads a runtime variable (always #(half) clk = ~clk) now re-evaluates its period every toggle, so a PLL reprogrammed at runtime actually changes frequency; verified against a commercial simulator alongside UDP primitives, tristate/pull strengths, specify/timing-check, and divider chains.
• Dead-clock watchdog — XEZIM_STUCK_CLOCK flags a process parked on a clock/reset that never changes while the design keeps churning edges (an undriven-net / dropped-cell hang), turning a silent multi-minute grind into an immediate, actionable diagnostic (warn by default; abort for CI).

xezim is split across two repos that live side by side; this repo depends on xezim-core via a relative path (../xezim-core) — it is a sibling directory, not a submodule:

../xezim-core/  — shared library: parser, elaboration, value, SDF, VCD sink (sibling repo)
./              — bytecode interpreter + simulator (this repo, binary: xezim)

This repo:

.
├── src/
│   ├── compiler/
│   │   ├── simulator.rs   — event-driven simulator + bytecode VM
│   │   ├── bytecode.rs    — bytecode compiler for cont_assigns and always blocks
│   │   └── mod.rs         — re-exports value/elaborate/sdf from xezim-core
│   ├── lib.rs             — wraps xezim_core::parse_and_elaborate_multi + Simulator
│   └── main.rs            — CLI entry point (binary: xezim)
├── tests/                 — Rust integration tests + SV compliance suite
├── examples/
└── Cargo.toml             — depends on xezim-core (path = ../xezim-core, a sibling repo)

Parser & elaboration — live in xezim-core; consumed by both xezim and xezim-b.

Simulator — event-driven VM over a bytecode lowering of cont_assigns and always blocks.

End-to-end TEST PASSED with bit-identical results vs the workloads' own golden expectations:

UVM run-phase (see docs/uvm-guide.md):

Full sv-tests run with the suite's own xezim runner (make report RUNNERS=Xezim), xezim 0.8.1. The generated HTML report and per-test CSV are checked in under reports/ (svtests_index.html, svtests_report.csv, and sv-tests-compliance.md).

An earlier run scored only 52 % because a -I library directory (ivtest/ivltests/, ~1000 mutually independent single-file tests) was scanned too eagerly: xezim honors IEEE §23.3.2 library semantics — an -I dir supplies module definitions to satisfy unresolved instantiations — but it was adopting every definition in the directory, so typedefs/enums from unrelated sibling files leaked into the primary design and failed a spurious §6.18 base-type check. resolve_library_modules now pulls in only the library modules actually reachable from the compiled design (transitively), which reclaimed ~1870 ivtest cases with no change to the native LRM/UVM results.

Many test cases are included to validate functionality.

Credit: All pr*.v tests were taken from the Icarus Verilog test suite.

These tests help verify correctness against real-world Verilog/SystemVerilog edge cases.

Install Rust: https://www.rust-lang.org/tools/install

This repo depends on xezim-core as a sibling directory (Cargo references it via path = "../xezim-core"), so clone both repos side by side into the same parent:

git clone git@github.com:<you>/xezim-core.git
git clone git@github.com:<you>/xezim.git
cd xezim

Expected layout:

<parent>/
├── xezim-core/   — shared library (parser, elaboration, value, SDF, VCD)
└── xezim/        — this repo (binary: xezim)

Build the simulator:

cargo build            # debug
cargo build --release  # optimized (recommended for large designs)

The release binary is produced at target/release/xezim.

Run a simple example via cargo:

cargo run --release -- examples/test.sv

Or invoke the binary directly:

./target/release/xezim <source_files> [+plusargs] [options]

Common options:

Selected env knobs (off by default unless noted):

Example — run the picorv32 testbench against a gate-level netlist:

./target/release/xezim testbench.v synth.v \
    +firmware=firmware/firmware.hex --max-time 50000000

Simulation mode stores a content-addressed elaborated design and compiled combinational worklist after the first run, then reuses both on identical later runs. A cache hit skips parsing, elaboration, and combinational dependency-index construction, while simulator state, plusargs, time-zero initialization, and event scheduling are rebuilt for every invocation. Timing-annotated and UDP designs conservatively rebuild the worklist. The key covers source and library contents, defines, include paths, top selection, language/strictness, timescale and delay settings, and the xezim executable build.

The default directory is $XEZIM_CACHE_DIR, then $XDG_CACHE_HOME/xezim/designs, then $HOME/.cache/xezim/designs. Use --cache-dir for a workload-local cache or --no-cache for a cold run. Xezim prints [CACHE] miss, [CACHE] stored, or [CACHE] hit on stderr.

--module-timescale is an xezim-specific command-line extension. It assigns a time unit and precision to module definitions that have no explicit source-level timescale, without changing the semantics of the source. It is handy for retrofitting a timescale onto legacy RTL that omits one, or onto a mix of files where only some carry `timescale.

# Every module without an explicit timescale gets 1ns/1ps:
xezim --module-timescale 1ns/1ps design.sv

# Only the listed definitions (comma-separated), 10ns/1ns:
xezim --module-timescale cpu,cache=10ns/1ns design.sv

# Repeatable; the named form wins over the global one:
xezim --module-timescale 1ns/1ps --module-timescale dram=1ps/1fs design.sv

A module has an explicit source-level timescale — which the option never overrides — when it has a timeunit/timeprecision declaration, or a `timescale directive is active where it is declared (`resetall clears that). Effective precedence, highest first:

1. module-local timeunit / timeprecision
2. an active `timescale directive
3. a named --module-timescale mods=<unit>/<prec>
4. a global --module-timescale <unit>/<prec>
5. the 1ns / 1ns default

The precision must be equal to or finer than the unit (1ns/1ps is legal, 1ps/1ns is an error). Two different named assignments for the same module are an error; an unmatched name, or one that lands on a module that already has an explicit timescale, is a warning (the assignment is ignored). Assignments apply to a definition, so every instance of it shares the timescale.

Sub-nanosecond precision is honoured — the simulation tick is the finest precision declared anywhere in the design, down to fs. (--max-time is counted in that tick, so a 1ps-precision design covers proportionally less wall-clock time for the same --max-time.)

--dump-timescales prints the resolved timescale of every module before the run — no source $printtimescale calls required. It reports each definition's `timescale semantics (an explicit/--module-timescale value, or the 1s/1s default when a module has none) and flags the modules that carry no `timescale. Combine it with --module-timescale to confirm an assignment landed where you intended.

$ xezim --dump-timescales design.sv
=== module timescales (3 modules) ===
  cache                        10ns / 1ns
  cpu                          1ns / 1ps
  glue                         1s / 1s   (no `timescale — 1s/1s default)
======================================

A flagged module also emits the has no timescale directive warning in a mixed-timescale design; give it a source `timescale or a --module-timescale assignment to resolve it. (The reported 1s/1s is the IEEE-default display value; such a module's effective delay unit is the design's global tick — a further reason to declare one explicitly.)

Typical development loop:

edit code
↓
cargo build
↓
run tests
↓
add new SystemVerilog features

Rust provides strong guarantees for memory safety and concurrency, making it well suited for building large-scale EDA infrastructure.

This project explores several long-term ideas:

• AI-assisted EDA development
• Rapid simulator prototyping
• Cloud-scale simulation
• Distributed multi-CPU simulation

The goal is to investigate whether modern software and AI tools can dramatically accelerate the creation of chip design infrastructure.

Apache License 2.0

See the LICENSE file for details.

xezim is developed in the open, and a number of people have improved it through pull requests. Thank you to everyone who has contributed — bug fixes, features, tests, and tooling all move the project forward:

• Thomas Burg — class-system and UVM fixes: static-property chains through object handles (§8.25), associative-array method dispatch and ref-writeback, ClassName::static_prop access, parser-gap self-tests, and test-harness hardening.
• Oscar Gustafsson — expanded VPI functionality (vpi_get_value, ObjectValType), CI setup, and clippy cleanups.
• Chen Ben Haroosh — submodule-inline generate-for elaboration: genvar- dependent declarations and parameter type default resolution, plus the accompanying SystemVerilog compliance cases.
• Jayaraman RP — cross-platform installation scripts, including the macOS installer with UVM setup.

New contributors are welcome — see Development Workflow.

• Icarus Verilog project for the public test suite
• The Rust community
• Open-source EDA projects