A GUI for managing Python virtual environments

Package manager and build system for VHDL, Verilog, and SystemVerilog

git-cola: The highly caffeinated Git GUI

Run legacy Cadsoft Eagle in Docker Container

A simple ring buffer (circular buffer) designed for embedded systems.

A Dissect module implementing a parser for C-like structures.

Enhanced version of Microchip PICkit2 software which supports PICkit2, PICkit3 and PKOB

Simple header-only C/C++ unit testing facility.

A Python package to use FPGA development tools programmatically.

Generator for CRC HDL code (VHDL, Verilog, MyHDL)

The original ELIZA on an emulated CTSS environment

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

AISLER support files

Software timers extend module for embedded

Library of open source Process Design Kits (PDKs)

An open-source HDL register code generator fast enough to run in real time.

GitHub Action for generating Doxygen documentation for your projects.

SPI Slave for TT05

Lightweight generic ring buffer manager library

Real-time embedded variable & trace viewer

A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.

🧪 single header unit testing framework for C and C++

The smallest public printf implementation for its feature set.

GNU toolchain for RISC-V, including GCC

This driver board controls e-paper displays from Waveshare. Thus it is easy to display visually beautiful dashboards.

The next generation of OpenLane, rewritten from scratch with a modular architecture