I spend most of my time in the gap between “test failed” and “here’s the exact cycle it broke.”
At Cadence, that means PCIe PHY, UVM regressions, coverage, logs, protocol traces, and plenty of SimVision. After hours, it’s RISC-V pipelines and self-checking testbenches.
Design Verification Intern @ Cadence · Jul 2025 → now
I work on PCIe Gen6/Gen7 Physical Layer verification—link training, LTSSM behavior, ordered sets, lane mapping and reversal, L0p, PCS timing, PIPE behavior, and the occasional failure that refuses to reproduce twice.
My usual loop:
triage → recreate → inspect logs/waves/traces → RTL, VIP, or TB? → rerun → green
SystemVerilog · UVM · Xcelium · SimVision · vManager
Current rabbit holes: forwarding priority, load-use bubbles, wrong-path flushes, and making sure every WB commit belongs to exactly one instruction.
IF → ID → EX → MEM → WB
Proof path: directed regressions · focused hazard test · assertions · coherent retirement trace
make test| Project | What I was chasing |
|---|---|
| UVM Memory Verification | Getting sequences, driver, monitor, analysis path, and scoreboard to agree on every read and write |
| Voting Machine RTL-to-GDS Lab | Following one Verilog design through Xcelium, Genus, Innovus, gate-level simulation, and Tempus STA |
B.Tech ECE · Jamia Millia Islamia ’25
Football / volleyball when the clocks stop.