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Yosys SystemVerilog Parser - UHDM 2 RTLIL Yosys Pass

Verilog 5 Updated Apr 6, 2026

Claude Code is an agentic coding tool that lives in your terminal, understands your codebase, and helps you code faster by executing routine tasks, explaining complex code, and handling git workflo…

Shell 118,337 19,681 Updated Apr 25, 2026

This is the development repository for the OpenFHE library. The current version is 1.5.1 (released on April 10, 2026).

C++ 1,114 288 Updated Apr 22, 2026

A compiler for homomorphic encryption

C++ 717 131 Updated Apr 27, 2026
Verilog 3 9 Updated Dec 2, 2024

Compiler backend from packing to bitstream generation.

C++ 7 4 Updated Dec 3, 2024

Raptor's GUI

C++ 5 7 Updated Dec 2, 2024

Raptor end-to-end FPGA Compiler and GUI

Verilog 96 26 Updated Dec 11, 2024

VHDL synthesis (based on ghdl)

VHDL 358 33 Updated Mar 14, 2026

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 2,615 872 Updated Apr 27, 2026

EPFL logic synthesis benchmarks

Verilog 244 45 Updated Mar 3, 2026

SystemVerilog to Verilog conversion

Haskell 725 62 Updated Mar 28, 2026

ABC: System for Sequential Logic Synthesis and Formal Verification

C 1,160 744 Updated Apr 26, 2026

Verilog to Routing -- Open Source CAD Flow for FPGA Research

C++ 1,221 441 Updated Apr 24, 2026

Yosys Open SYnthesis Suite

C++ 4,420 1,071 Updated Apr 27, 2026

Framework Open EDA Gui

C++ 74 33 Updated Dec 11, 2024

Modular hardware build system

Python 1,153 128 Updated Apr 27, 2026

An Open-source FPGA IP Generator

Verilog 1,090 198 Updated Apr 27, 2026

SystemVerilog synthesis tool

Verilog 232 29 Updated Mar 10, 2025

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

Java 18,836 3,435 Updated Feb 16, 2026

Build your hardware, easily!

Python 3,850 705 Updated Apr 27, 2026

Plugins for Yosys developed as part of the F4PGA project.

Verilog 84 49 Updated May 14, 2024

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

C++ 458 79 Updated Apr 5, 2026

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog 375 90 Updated Apr 24, 2026

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VHDL 708 66 Updated Dec 14, 2025

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

C++ 26 4 Updated Apr 5, 2026

A beautiful stack trace pretty printer for C++

C++ 4,275 529 Updated Apr 14, 2025

Cap'n Proto serialization/RPC system - core tools and C++ library

C++ 13,002 1,047 Updated Apr 24, 2026

FlatBuffers: Memory Efficient Serialization Library

C++ 25,842 3,552 Updated Apr 18, 2026

Ideas that need engineering-power from the community for UHDM/Surelog/Related topics

2 Updated Oct 14, 2020
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