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Showing results

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Python 3,726 488 Updated Jul 21, 2026

SERV - The SErial RISC-V CPU

Verilog 1,887 264 Updated Aug 25, 2026

VHDL implementation of Pipelined Wishbone B4 interconnect

VHDL 3 1 Updated Dec 5, 2024

A study of soft-core CPUs for use with FPGA designs

Verilog 2 Updated Dec 6, 2024

Small portable AES128/192/256 in C

C 5,006 1,395 Updated Oct 4, 2024