PicoRV32 - A Size-Optimized RISC-V CPU

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

The Ultra-Low Power RISC-V Core

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Standard Cell Library based Memory Compiler using FF/Latch cells

FPGA Logic Analyzer and GUI

JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.

A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.

FFT implement by verilog_测试验证已通过

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

tinyVision.ai Vision & Sensor FPGA System on Module

Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.

FFT implementation using CORDIC algorithm written in Verilog.

Verilog code for a circuit implementation of Radix-2 FFT

SystemVerilog files for lab project on a DNN hardware accelerator

Digital Design Lab Spring 2019 Final Project

A 3-stage in-order single-scalar RISC-V processor

This is a project to implement a Neural Network Model with descent functionality

An NPU designed using an LLM with a single prompt

Different DNNWeaver simulation setups

OpenROAD's unified application implementing an RTL-to-GDS Flow