Wireshark dissector for the NDFEX protocol

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

ao486 port for MiSTer

OpenXuantie - OpenC910 Core

Wolv Z7 is a RISC-V CPU core with floating point unit

Core generation scripts for various FPGA boards

BBC Micro B and Master 128K for MiSTer

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

32-bit Superscalar RISC-V CPU

Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

SPIR-V fragment shader GPU core based on RISC-V

Macintosh SE Hardware Designs

3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.

Marginally better than redstone

Apple II+ for MiSTer

port of HT1080Z to MiSTer (Tandy TRS-80 Model I)

GBA for MiSTer

Macintosh Plus for MiSTer

Verilog Ethernet components for FPGA implementation

FX68K 68000 cycle accurate SystemVerilog core

Xilinx PCIe to MIG DDR4 example designs and custom part data files

FPGA foodfight arcade game in verilog