SnowSakura_31.5ns_Labs in HKEX-OMD-C

Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.

git clone of http://code.google.com/p/axi-bfm/

FIX request-response latency using eBPF TC hooks

Verilog PCI express components

Wireshark dissector for the NDFEX protocol

Class projects for High-Frequency Trading Technologies at the University of Notre Dame

FPGA and Digital ASIC Build System

Open Logic FPGA Standard Library

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

Config files for my GitHub profile.

Open-source RTL logic simulator with CUDA acceleration

RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm

An rv32i inspired ISA, SIMT GPU implementation in system-verilog.

Library defining all Ethernet packets in SystemVerilog and in SystemC

System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers

Verilog Ethernet components for FPGA implementation

Open source ISS and logic RISC-V 32 bit project

TCP Offload Engine

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

A SystemC productivity library: https://minres.github.io/SystemC-Components/

contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols