Verilog Ethernet components for FPGA implementation

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Open source FPGA-based NIC and platform for in-network compute

Must-have verilog systemverilog modules

32-bit Superscalar RISC-V CPU

An Open-source FPGA IP Generator

A tiny Open POWER ISA softcore written in VHDL 2008

A High-performance Timing Analysis Tool for VLSI Systems

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

Verilog Configurable Cache

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

Advanced Interface Bus (AIB) die-to-die hardware open source

Introductory course into static timing analysis (STA).