ABC: System for Sequential Logic Synthesis and Formal Verification

Frontend for freehdl

VHDL 2008/93/87 simulator

Icarus Verilog

Yosys Open SYnthesis Suite

A Python toolbox for building complex digital hardware

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

nextpnr portable FPGA place and route tool

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

An abstraction library for interfacing EDA tools

Open FPGA tools

VHDL 2008/93/87 simulator

This linter plugin for SublimeLinter provides an interface to 'ghdl' for VHDL linting.

This linter plugin for SublimeLinter provides an interface to 'ghdl' for VHDL linting.

This linter plugin for SublimeLinter provides an interface to 'ghdl' for VHDL linting.

Atom vhdl linter

Atom vhdl linter

Documenting the Lattice ECP5 bit-stream format.

Documenting the Xilinx 7-series bit-stream format.

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the fut…

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