Synchronous FIFOs designed in Verilog/System Verilog.

hardware（scopefun 双通道虚拟示波器，基于 Kicad 的 PCB 工程）

Scopefun FPGA source code（scopefun 双通道虚拟示波器，FPGA 底层实现）

irig_b encode and decode

Firmware IRIG-B decoder

include hdlc (miao), 422 grapher, 1553b

development interface mil-std-1553b for system on chip

A simulator for 1553B protocol, based on BU-61580 protocol card

JSON lib in Systemverilog

PCIe library for the Xilinx 7 series FPGAs in the Bluespec language

Example designs for FPGA Drive FMC

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

Style guide enforcement for VHDL

This is a tool to check various rules of a digital design written in verilog HDL. This tool uses Icarus Verilog APIs

Visual Studio Code

Different examples showing how to use ghdl

Repurposing existing HDL tools to help writing better code

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

VHDL compiler and simulator

Qucs Project official mirror

Frontend for freehdl

GUI for SymbiYosys

Example LED blinking project for your FPGA dev board of choice

A High-performance Timing Analysis Tool for VLSI Systems

An Open-source FPGA IP Generator

Open-source FPGA research and prototyping framework.