Nix Packages collection & NixOS

Open-source high-performance RISC-V processor

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

Open Logic FPGA Standard Library

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Communication framework for RTL simulation and emulation.

Verilator open-source SystemVerilog simulator and lint system

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

XLS: Accelerated HW Synthesis

Data Structures and Algorithms library with strong emphasis on functional programming

The official repository for the gem5 computer-system architecture simulator.

Spike, a RISC-V ISA Simulator

SystemVerilog compiler and language services

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

ASIC implementation flow infrastructure, successor to OpenLane

Build your hardware, easily!

Universal utility for programming FPGA

GNU toolchain for RISC-V, including GCC

An abstraction library for interfacing EDA tools

Network on Chip Simulator

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

A dependency management tool for hardware projects.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Rocket Chip Generator