55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.

Strided Data Prefetcher for High-Performance Cache Hierarchies

ASIC implementation flow infrastructure, successor to OpenLane

An open-source static random access memory (SRAM) compiler.

UVM Verification Environment for the CVFPU

Coverview

PolyBench/C benchmark suite (version 4.2.1 beta) from http://web.cse.ohio-state.edu/~pouchet/software/polybench/

The official repository for the gem5 computer-system architecture simulator.

A SystemVerilog source file pickler.

fakeram generator for use by researchers who do not have access to commercial ram generators

Nix Packages collection & NixOS

SystemVerilog compiler and language services

SystemVerilog IPs and Modules for architectural redundancy designs.

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

Home of the open-source EDA course.

Open Application-Specific Instruction Set processor tools (OpenASIP)

An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders

RISC-V IOMMU Specification

Package manager and build abstraction tool for FPGA/ASIC development

A dependency management tool for hardware projects.

Network on Chip Simulator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

Containing dozens of real-world and synthetic tests, CoreMark®-PRO (2015) is an industry-standard benchmark that measures the multi-processor performance of central processing units (CPU) and embed…

Modified version of the STREAM benchmark with multi-node support via MPI and OpenSHMEM and irregular memory access patterns.