Researcher on computer architecture, digital hardware designer and processor architect.
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Inria, TIMA Laboratory, University Grenoble Alpes
- Grenoble, France
- https://www.linkedin.com/in/cesar-fuguet/
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The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register i…