Verilator open-source SystemVerilog simulator and lint system

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

The root repo for lowRISC project and FPGA demos.

A simple superscalar out-of-order RISC-V microprocessor

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

SystemVerilog IPs and Modules for architectural redundancy designs.

Strided Data Prefetcher for High-Performance Cache Hierarchies