Skip to content
View cfuguet's full-sized avatar

Block or report cfuguet

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
8 stars written in Verilog
Clear filter

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 2,337 749 Updated Dec 21, 2025

OpenXuantie - OpenC910 Core

Verilog 1,359 362 Updated Jun 28, 2024

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Verilog 308 93 Updated Dec 20, 2025

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.

Verilog 143 17 Updated Dec 17, 2025

Reconfigurable Computing Lab, DESE, Indian Institiute of Science

Verilog 27 4 Updated Jun 22, 2024

Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process

Verilog 19 6 Updated Mar 30, 2025
Verilog 4 Updated Mar 10, 2025
Verilog 3 2 Updated Oct 27, 2025