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7 results for source starred repositories written in Verilog
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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 2,412 779 Updated Feb 3, 2026

OpenXuantie - OpenC910 Core

Verilog 1,387 370 Updated Jun 28, 2024

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Verilog 317 94 Updated Feb 3, 2026

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.

Verilog 167 19 Updated Dec 29, 2025

Reconfigurable Computing Lab, DESE, Indian Institiute of Science

Verilog 27 4 Updated Jun 22, 2024

Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process

Verilog 19 6 Updated Mar 30, 2025
Verilog 4 Updated Mar 10, 2025