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56 results for source starred repositories
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Basic PCells, DRC, LVS, XSection for Sky130A technology

Python 10 2 Updated Jun 10, 2024

wafer.space GF180MCU Run 1

8 Updated Jan 20, 2026

Blender GDSII Importer with PDK Support

Python 78 7 Updated Jan 28, 2026

A Python library for designing chips (Photonics, Analog, Quantum, MEMS), PCBs, and 3D-printable objects. We aim to make hardware design accessible, intuitive, and fun—empowering everyone to build t…

Python 843 355 Updated Feb 4, 2026

100kHz to 6GHz 2 port USB based VNA

C++ 1,459 256 Updated Jan 27, 2026

3D finite element solver for computational electromagnetics

C++ 454 88 Updated Feb 7, 2026

RFIC EM simulation: Create AWS Palace model from GDSII layout files

Python 35 6 Updated Feb 3, 2026

Tiny Tapeout SKY 25a shuttle on ChipFoundry CC2509 MPW

Verilog 3 6 Updated Nov 25, 2025

A FABulous FPGA utilizing the Panamax padframe

Verilog 10 Updated Aug 10, 2025

KLayout plugin for efficient alignments of layout objects

Python 10 2 Updated Dec 17, 2025

Development repository for openEMS workflow for IHP SG13G2

Python 59 6 Updated Feb 4, 2026

Python interface to OpenEMS, for PCB trace simulation. Accepts Gerber files as input. Features automatic grid generation and postprocessing.

Python 198 29 Updated Jan 30, 2026

Parasitic Extraction for KLayout

Python 39 10 Updated Feb 3, 2026

OpenVAF revived by community

Rust 21 4 Updated Jul 21, 2025

Gm over Id methodology

36 4 Updated Jun 8, 2022

The Xyce™ Parallel Electronic Simulator

C 113 13 Updated Jan 26, 2026

Raw data collected about the SKY130 process technology.

Jupyter Notebook 61 18 Updated May 7, 2023

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called pr…

C++ 247 39 Updated Aug 20, 2024

12 bit SAR ADC IP in Skywater 130 nm PDK

C 24 4 Updated May 30, 2024

Files for Advanced Integrated Circuits

Makefile 36 8 Updated Jan 17, 2026

Extra backend checks for sky130

Shell 10 7 Updated Dec 16, 2025

Project F brings FPGAs to life with exciting open-source designs you can build on.

SystemVerilog 746 70 Updated Jan 28, 2026

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Python 1,129 235 Updated Sep 22, 2025

Hardware Design Tool - Mixed Signal Simulation with Verilog

Python 89 7 Updated Dec 18, 2024

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,933 893 Updated Jun 27, 2024

A simple RISC V core for teaching

SystemVerilog 201 23 Updated Dec 30, 2021
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