100kHz to 6GHz 2 port USB based VNA

3D finite element solver for computational electromagnetics

RFIC EM simulation: Create AWS Palace model from GDSII layout files

Tiny Tapeout SKY 25a shuttle on ChipFoundry CC2509 MPW

A FABulous FPGA utilizing the Panamax padframe

KLayout plugin for efficient alignments of layout objects

Development repository for openEMS workflow for IHP SG13G2

Python interface to OpenEMS, for PCB trace simulation. Accepts Gerber files as input. Features automatic grid generation and postprocessing.

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Parasitic Extraction for KLayout

OpenVAF revived by community

Gm over Id methodology

The Xyce™ Parallel Electronic Simulator

Raw data collected about the SKY130 process technology.

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called pr…

12 bit SAR ADC IP in Skywater 130 nm PDK

Low-power operational amplifier by Luis Henrique Rodovalho (Chipalooza challenge 2024)

Files for Advanced Integrated Circuits

Extra backend checks for sky130

Project F brings FPGAs to life with exciting open-source designs you can build on.

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Hardware Design Tool - Mixed Signal Simulation with Verilog

PicoRV32 - A Size-Optimized RISC-V CPU

A simple RISC V core for teaching

Verilog-A simulation models

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

Terminal file manager