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  • PEZY Computing K.K.
  • Kanagawa, Japan
  • 22:36 (UTC +09:00)
  • X @dalance1982

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⚓ GROWI - Team collaboration software using markdown

TypeScript 1,442 239 Updated Mar 24, 2026

Like Prometheus, but for logs.

Go 27,858 3,962 Updated Mar 24, 2026

LL(k) and LALR(1) parser generator for Rust and C#

Rust 233 19 Updated Mar 24, 2026

Empowering everyone to build reliable and efficient software.

Rust 111,453 14,667 Updated Mar 24, 2026

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog 368 88 Updated Mar 24, 2026

Filelist generator

Ruby 20 1 Updated Mar 23, 2026

A terminal workspace with batteries included

Rust 30,356 1,050 Updated Mar 23, 2026

A code coverage tool for Rust projects

Rust 2,939 193 Updated Mar 23, 2026

🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl

Rust 92 17 Updated Mar 22, 2026

A cross-platform, OpenGL terminal emulator.

Rust 63,095 3,360 Updated Mar 21, 2026

Gain deeper insights into your favourite open-source GitHub repositories. Explore star trends showing daily stats.

JavaScript 335 11 Updated Mar 20, 2026

Cargo subcommand to easily use LLVM source-based code coverage (-C instrument-coverage).

Rust 1,322 79 Updated Mar 20, 2026

Basic Common Modules

SystemVerilog 46 8 Updated Mar 18, 2026

Language Server Protocol implementation for Rust based on Tower

Rust 184 20 Updated Mar 14, 2026

Code generation tool for control and status registers

Ruby 450 57 Updated Mar 14, 2026

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

C++ 1,795 275 Updated Mar 13, 2026

Cargo subcommand `release`: everything about releasing a rust crate.

Rust 1,545 127 Updated Mar 13, 2026
SystemVerilog 11 2 Updated Mar 9, 2026

GitHub Action for continuous benchmarking to keep performance

TypeScript 1,203 182 Updated Mar 2, 2026

Translation support for mdbook. The plugins here give you a structured way to maintain a translated book.

Rust 206 38 Updated Mar 2, 2026

RSD: RISC-V Out-of-Order Superscalar Processor

SystemVerilog 1,158 116 Updated Feb 21, 2026

bluecore - risc-v cpu

Python 10 1 Updated Feb 13, 2026

Let's write RISC-V CPU in Veryl!

Reason 63 2 Updated Feb 12, 2026

Hardware WebAssembly processor in Veryl HDL

Rust 6 Updated Feb 9, 2026
Ruby 4 1 Updated Feb 3, 2026

Graph the number of crates that depend on your crate over time

Rust 256 11 Updated Feb 2, 2026

An asynchronous, runtime data feedable terminal paging library for Rust

Rust 361 29 Updated Dec 22, 2025

This crate provides useful tools to generate multiple readable passwords, as well as analyze and score them.

Rust 44 6 Updated Nov 24, 2025

Meno is a tool for visualizing hierarchical data, such as synthesized circuit sizes. It can be built into a single, standalone HTML file. Currently, Meno supports hierarchical area reports from Viv…

TypeScript 20 5 Updated Nov 3, 2025
TypeScript 442 20 Updated Oct 27, 2025
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